1 radiation hardened quad voltage comparator hs-139rh, HS-139EH the radiation hardened hs-139rh, HS-139EH consists of four independent single or dual su pply voltage comparators on a single monolithic substrate. the common mode input voltage range includes ground, even when operated from a single supply and the low supply current makes these comparators suitable for low power applications. these types were designed to directly interface with ttl and cmos. the hs-139rh, HS-139EH are fabricated on our dielectrically isolated rad hard silicon gate (rsg) process, which provides an immunity to single event latch-up and the capability of highly reliable performance in any radiation environment. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbers listed below must be used when ordering. detailed electrical specificatio ns for the hs-139rh, HS-139EH are contained in smd 5962-98613 . a ?hot-link? is provided on our homepage with instructions for downloading. www.intersil.com/spacedefense/newsafclasst.asp features ? qml qualified per mil-prf-38535 requirements ?radiation environment - latch-up free under any conditions - total dose (max) . . . . . . . . . . . . . . . . . . . . . . 3 x 10 5 rad(si) - seu let threshold . . . . . . . . . . . . . . . . . . . 20mev/cm 2 /mg - low dose rate effects immunity ? 100v output voltage withstand capability ? esd protection to >3000v ? differential input voltage range equal to the supply voltage ? input offset voltage (v io ). . . . . . . . . . . . . . . . . . . . . 2mv (max) ? quiescent supply current . . . . . . . . . . . . . . . . . . . . 2ma (max) ? pb-free (rohs compliant) applications ?pulse generators ? timing circuitry ?level shifting ? analog-to-digital conversion pin configurations hs-139rh, HS-139EH (sbdip cdip2-t14) top view hs-139rh, HS-139EH (flatpack cdfp3-f14) top view out 2 out 1 v+ - in 1 + in 1 - in 2 + in 2 out 3 out 4 gnd + in 4 - in 4 + in 3 - in 3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 14 13 12 11 10 9 8 2 3 4 5 6 7 1 out 2 out 1 v+ - in 1 + in 1 - in 2 +in 2 out 3 out 4 gnd + in 4 - in 4 + in 3 - in 3 august 8, 2013 fn3573.6 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 1999, 2004, 2008, 2009, 2012, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
hs-139rh, HS-139EH 2 fn3573.6 august 8, 2013 ordering information ordering smd number (note 1 ) part number (note 2 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # 5962f9861303vcc hs1-139eh-q q 5962f98 61303vcc -55 to +125 14 ld sbdip d14.3 5962f9861301vcc hs1-139rh-q q 5962f98 61301vcc -55 to +125 14 ld sbdip d14.3 5962f9861301qcc hs1-139rh-8 q 5962f98 61301qcc -55 to +125 14 ld sbdip d14.3 hs1-139rh/proto hs1-139rh/proto hs1-139rh/proto -55 to +125 14 ld sbdip d14.3 5962f9861301vxc hs9-139rh-q q 5962f98 61301vxc -55 to +125 14 ld flatpack k14.a 5962f9861301qxc hs9-139rh-8 q 5962f98 61301qxc -55 to +125 14 ld flatpack k14.a 5962f9861303vxc hs9-139eh-q q 5962f98 61303vxc -55 to +125 14 ld flatpack k14.a hs9-139rh/proto hs9-139rh/proto hs9-139rh /proto -55 to +125 14 ld flatpack k14.a 5962f9861303v9a hs0-139eh-q -55 to +125 die 5962f9861301v9a hs0-139rh-q -55 to +125 die hs0-139rh/sample hs0-139rh/sample -55 to +125 die notes: 1. specifications for rad hard qml devices are controlled by the de fense logistics agency land and maritime (dla). the smd numbers listed in the ?ordering information? table on page 2 must be used when ordering. 2. these intersil pb-free hermetic packaged produc ts employ 100% au plate - e4 termination finish, which is rohs compliant and c ompatible with both snpb and pb-free soldering operations.
hs-139rh, HS-139EH 3 fn3573.6 august 8, 2013 die characteristics die dimensions: 3750m x 2820m (148 mils x 111 mils) 483m 25.4m (19 mils 1 mil) interface materials: glassivation: type: silox (sio 2 ) thickness: 8.0k? 1.0k? top metallization: type: alsicu thickness: 16.0k? 2k? substrate: radiation hardened silicon gate, dielectric isolation backside finish: silicon assembly related information: substrate potential: unbiased (di) additional information: worst case current density: <2.0 x 10 5 a/cm 2 transistor count: 49 metallization mask layout hs-139rh, HS-139EH gnd +in4 -in4 v+ -in1 +in1 +in3 -in3 +in2 -in2 out4 out3 out2 out1 (9) (8) (7) (6) (5) (4) (3) (2) (1) (14) (13) (12) (11) (10)
hs-139rh, HS-139EH 4 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn3573.6 august 8, 2013 for additional products, see www.intersil.com/product_tree table 1. hs-139rh, HS-139EH pad coordinates relative to pin 1 pin number pad name x coordinates y coordinates 1 out 2 0 0 2 out 1 0 -535 3 v+ 1323 -688 4 -in 1 1862 -670 5 +in 1 2439 -670 6 -in 2 3084 -299 7 +in 2 3084 278 8 -in 3 3084 518 9 +in 3 3084 1095 10 -in 4 2439 1466 11 +in 4 1862 1466 12 gnd 1550 1503 13 out 4 0 1331 14 out 3 0 796 note: dimensions in microns
hs-139rh, HS-139EH 5 fn3573.6 august 8, 2013 ceramic dual-in-line me tal seal packages (sbdip) notes: 3. index area: a notch or a pin one id entification mark shall be located adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identific ation shall not be used as a pin one identification mark. 4. the maximum limits of lead dime nsions b and c or m shall be mea - sured at the centroid of the fini shed lead surfaces, when solder dip or tin plate lead finish is applied. 5. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 6. corner leads (1, n, n/2, and n/2+1) may be configured with a par - tial lead paddle. for this configur ation dimension b3 replaces di - mension b2. 7. dimension q shall be measured from the seating plane to the base plane. 8. measure dimension s1 at all four corners. 9. measure dimension s2 from the top of the ceramic body to the near - est metallization or lead. 10. n is the maximum number of terminal positions. 11. braze fillets shall be concave. 12. dimensioning and tolerancing per ansi y14.5m - 1982. 13. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d14.3 mil-std-1835 cdip2-t14 (d-1, configuration c) 14 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.785 - 19.94 - e 0.220 0.310 5.59 7.87 - e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n 14 14 8 rev. 0 4/94
hs-139rh, HS-139EH 6 fn3573.6 august 8, 2013 ceramic metal seal fl atpack packages (flatpack) notes: 1. index area: a notch or a pin one id entification mark shall be located adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identific ation shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. this dimension allows for off-c enter lid, meniscus, and glass over - run. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish th ickness. the maximum limits of lead dimensions b and c or m shal l be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric materi - als shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the me - niscus) of the lead from the bo dy. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k14.a mil-std-1835 cdfp3-f14 (f-2a, configuration b) 14 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.390 - 9.91 3 e 0.235 0.260 5.97 6.60 - e1 - 0.290 - 7.11 3 e2 0.125 - 3.18 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.270 0.370 6.86 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 - 6 m - 0.0015 - 0.04 - n 14 14 - rev. 0 5/18/94
|
